Dynamic Random Access Memory Errors Correction DRAM ECC. Because soft errors are extremely common in the DRAM of computers used in satellites and space probes, such memory is structured as ECC memory. Typically every bit of memory is refreshed at least 15 times per second. During this memory refresh, the memory controller reads each word of memory and writes the (corrected) word back. Such memory controllers traditionally use a Hamming code. Even though a single cosmic ray can upset many physically neighboring bits in a DRAM, such memory systems are designed so that neighboring bits belong to different words, can be corrected by a single-bit error correcting code. As long as no more than a single bit in any particular word is hit by an error between refreshes, such a memory system presents the illusion of an error-free memory. ECC memory provides greater data accuracy and system uptime by protecting against soft errors in computer memory.