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Premium 1GB DDR 333 PC2700 200-Pin Notebook SODIMM

List Price: $42.99
Sale Price: $39.15
QTY.
Quantity Price
1 - 2 $39.15
3 - 9 $38.17
10 - 24 $37.98
25 - 49 $37.78
50 - 99 $37.58
100 + $37.58
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This product eligible for FREE shipping on orders above $50.00 (restrictions apply)
Availability:
1-2 Days
Shipping: from $2.99 Shipping Calculator
Manufacturer: Premium
Mfr Part #: D333SB1G/V
Product SKU: HV4956
Package: Bulk
Condition: New
more info...
Not sure what memory you need? Let us match the exact memory for your system!
Please use our Memory Match Maker™ to tell us about the RAM currently installed on your computer and we will back with our RAM suggestions for you from a few minutes to one hour or next day if submitted after business hours.
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Additional DDR-333 PC-2700 Products
Select Products
1GB DDR 333 PC2700 200-Pin Notebook SODIMM 1GB DDR 333 PC2700 200-Pin Notebook SODIMM
$42.50
$38.40
512MB DDR 333 PC2700 200-Pin Notebook SODIMM 512MB DDR 333 PC2700 200-Pin Notebook SODIMM
$24.45
$22.45
Premium 512MB DDR 333 PC2700 200-Pin Notebook SODIMM Premium 512MB DDR 333 PC2700 200-Pin Notebook SODIMM
$25.95
$22.85
number of selected products:
0
total main product + selected:
$39.15
 
When it comes to upgrading your laptop memory, you can't go wrong with 200-PIN DDR Memory. This varying-speed memory is not only backwards-compatible with all 200-PIN DDR Laptops, but its durability and industry standard reputation will ensure you are getting the most reliable upgrade. Give your computer that extra performance boost it needs with 200-PIN DDR chips.
  200-Pin SODIMM (Dual In-Line Memory) Module
Pins: 200-PIN
Plating: Gold Plated PINS
  Serial Presence Detect with Write Protect Feature
Voltage: 2.5V
CL (CAS Latency): 2.5
Clock Frequency: 333Mhz (PC2700)
Clock Access Time: 6ns
  Phase-lock loop (PLL) clock driver to reduce loading
Chip Configuration: 32 x 8
  • Commands entered on each positive CK edge
  • DQS edge-aligned with data for READs; center-aligned with data for WRITEs
  • Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle
  • Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture
  • Differential clock inputs (CK0 and CK0#)
  • Four internal banks for concurrent operation
  • Programmable burst lengths: 2, 4, or 8
  • Auto precharge option
  • Auto Refresh and Self Refresh Modes
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